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this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 1 en29lv320a rev. b, issue date: 2007 / 07 / 17 features ? single power supply operation - full voltage range: 2.7 to 3.6 volts read and write operations ? high performance - access times as fast as 70 ns ? low power consumption (typical values at 5 mhz) - 9 ma typical active read current - 20 ma typical program/erase current - less than 1 a current in standby or automatic sleep mode. ? flexible sector architecture: - eight 8-kbyte sectors, sixty-three 64k-byte sectors. - 8-kbyte sectors for top or bottom boot. - sector/sector group protection: hardware locking of sectors to prevent program or erase operations within individual sectors additionally, temporary sector group unprotect allows code changes in previously locked sectors. ? high performance program/erase speed - word program time: 8s typical - sector erase time: 500ms typical - chip erase time: 70s typical ? jedec standard compatible ? standard data# polling and toggle bits feature ? unlock bypass program command supported ? erase suspend / resume modes: read and program another sector during erase suspend mode ? support jedec common flash interface (cfi). ? low vcc write inhibit < 2.5v ? minimum 100k program/erase endurance cycles. ? reset# hardware reset pin - hardware method to reset the device to read mode. ? wp#/acc input pin - write protect (wp#) function allows protection of outermost two boot sectors, regardless of sector protect status - acceleration (acc) function provides accelerated program times ? package options - 48-pin tsop (type 1) - 48 ball 6mm x 8mm fbga ? commercial and industrial temperature range. general description the en29lv320a is a 32-megabit, electrically erasable, read/write non-volatile flash memory, organized as 4,194,304 bytes or 2.097,152 words. any word can be programmed typically in 8s. the en29lv320a features 3.0v voltage read and write operation, with access times as fast as 70ns to eliminate the need for wait states in high-performance microprocessor systems. the en29lv320a has separate output enable (oe#), chip enable (ce#), and write enable (we#) controls, which eliminate bus contention issues. this device is designed to allow either single sector or full chip erase operation, where each sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. the device can sustain a minimum of 100k program/erase cycles on each sector. . en29lv320a 32 megabit (4096k x 8-bit / 2048k x 16-bit) flash memory boot sector flash memory, cmos 3.0 volt-only
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 2 en29lv320a rev. b, issue date: 2007 / 07 / 17 connection diagrams a6 a5 a4 a1 a3 a2 fbga top view, balls facing down a13 a9 a3 ry/by# we# a7 b6 b5 b4 b1 b3 b2 a12 a8 a4 wp# /acc reset# a17 c6 c5 c4 c1 c3 c2 a14 a10 a2 a18 nc a6 d6 d5 d4 d1 d3 d2 a15 a11 a1 a20 a19 a5 e6 e5 e4 e1 e3 e2 a16 dq7 a0 dq2 dq5 dq0 f6 f5 f4 f3 f2 byte# dq14 ce# dq10 dq12 dq8 g6 g5 g4 g3 g2 dq15/a-1 dq13 oe# dq11 vcc dq9 h6 h5 h3 h2 vss dq6 vss dq4 dq1 f1 g1 h4 h1 dq3
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 3 en29lv320a rev. b, issue date: 2007 / 07 / 17 table 1. pin description logic diagram pin name function a0-a20 21 address inputs dq0-dq14 15 data inputs/outputs dq15 / a-1 dq15 (data input/out put, in word mode), a-1 (lsb address input, in byte mode) ce# chip enable oe# output enable we# write enable wp#/acc write protec t / acceleration pin reset# hardware reset pin byte# byte/word mode selection ry/by# ready/busy output vcc supply voltage (2.7-3.6v) vss ground nc not connected to anything en29 lv320 dq0 ? dq15 (a-1) a0 ? a20 ce# ry/by# reset# byte# wp#/acc oe# we#
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 4 en29lv320a rev. b, issue date: 2007 / 07 / 17 ordering information en29lv320a t 70 t c p packaging content (blank) = conventional p = pb free temperature range c = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) package t = 48-pin tsop b = 48-ball fine pitch ball grid array (fbga) 0.80mm pitch, 6mm x 8mm pa ckage speed 70 = 70ns 90 = 90ns boot code sector architecture t = top boot sector b = bottom boot sector base part number en = eon silicon solution inc. 29lv = flash, 3v read, program and erase 320a = 32 megabit (4m x 8 / 2m x 16)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 5 en29lv320a rev. b, issue date: 2007 / 07 / 17 u table 2a. top boot sector address tables (en29lv320at) sector a20 ? a12 sector size (kbytes / kwords) address range (h) byte mode (x8) address range (h) word mode (x16) sa0 000000xxx 64/32 00000 0?00ffff 000 000?007fff sa1 000001xxx 64/32 01000 0?01ffff 008000?00ffff sa2 000010xxx 64/32 02000 0?02ffff 010 000?017fff sa3 000011xxx 64/32 03000 0?03ffff 018000?01ffff sa4 000100xxx 64/32 04000 0?04ffff 020 000?027fff sa5 000101xxx 64/32 05000 0?05ffff 028000?02ffff sa6 000110xxx 64/32 06000 0?06ffff 030 000?037fff sa7 000111xxx 64/32 07000 0?07ffff 038000?03ffff sa8 001000xxx 64/32 08000 0?08ffff 040 000?047fff sa9 001001xxx 64/32 09000 0?09ffff 048000?04ffff sa10 001010xxx 64/32 0a00 00?0affff 050000?057fff sa11 001011xxx 64/32 0b00 00?0bffff 058000?05ffff sa12 001100xxx 64/32 0c000 0?0cffff 060 000?067fff sa13 001101xxx 64/32 0d000 0?0dffff 068000?06ffff sa14 001110xxx 64/32 0e00 00?0effff 070000?077fff sa15 001111xxx 64/32 0f000 0?0fffff 078000?07ffff sa16 010000xxx 64/32 10000 0?10ffff 080 000?087fff sa17 010001xxx 64/32 11000 0?11ffff 088000?08ffff sa18 010010xxx 64/32 12000 0?12ffff 090 000?097fff sa19 010011xxx 64/32 13000 0?13ffff 098000?09ffff sa20 010100xxx 64/32 140000?14ffff 0a 0000?0a7fff sa21 010101xxx 64/32 150000?15ffff 0a 8000?0affff sa22 010110xxx 64/32 160000?16ffff 0b 0000?0b7fff sa23 010111xxx 64/32 170000?17ffff 0b 8000?0bffff sa24 011000xxx 64/32 180000?18ffff 0c 0000?0c7fff sa25 011001xxx 64/32 190000?19ffff 0c 8000?0cffff sa26 011010xxx 64/32 1a0000?1 affff 0d0000?0d7fff sa27 011011xxx 64/32 1b0000?1 bffff 0d8000?0dffff sa28 011100xxx 64/32 1c0000?1 cffff 0e0000?0e7fff sa29 011101xxx 64/32 1d0000?1 dffff 0e8000?0effff sa30 011110xxx 64/32 1e0000?1 effff 0f0000?0f7fff sa31 011111xxx 64/32 1f0000?1 fffff 0f8000?0fffff sa32 100000xxx 64/32 2000 00?20ffff 100 000?107fff sa33 100001xxx 64/32 2100 00?21ffff 108000?10ffff sa34 100010xxx 64/32 2200 00?22ffff 110 000?117fff sa35 100011xxx 64/32 2300 00?23ffff 118000?11ffff sa36 100100xxx 64/32 2400 00?24ffff 120 000?127fff sa37 100101xxx 64/32 2500 00?25ffff 128000?12ffff
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 6 en29lv320a rev. b, issue date: 2007 / 07 / 17 sa38 100110xxx 64/32 2600 00?26ffff 130 000?137fff sa39 100111xxx 64/32 2700 00?27ffff 138000?13ffff sa40 101000xxx 64/32 2800 00?28ffff 140 000?147fff sa41 101001xxx 64/32 2900 00?29ffff 148000?14ffff sa42 101010xxx 64/32 2a00 00?2affff 150000?157fff sa43 101011xxx 64/32 2b00 00?2bffff 158000?15ffff sa44 101100xxx 64/32 2c00 00?2cffff 160 000?167fff sa45 101101xxx 64/32 2d00 00?2dffff 168000?16ffff sa46 101110xxx 64/32 2e00 00?2effff 170000?177fff sa47 101111xxx 64/32 2f00 00?2fffff 178000?17ffff sa48 110000xxx 64/32 3000 00?30ffff 180 000?187fff sa49 110001xxx 64/32 3100 00?31ffff 188000?18ffff sa50 110010xxx 64/32 3200 00?32ffff 190 000?197fff sa51 110011xxx 64/32 3300 00?33ffff 198000?19ffff sa52 110100xxx 64/ 32 340000?34ffff 1a0000?1a7fff sa53 110101xxx 64/ 32 350000?35ffff 1a8000?1affff sa54 110110xxx 64/ 32 360000?36ffff 1b0000?1b7fff sa55 110111xxx 64/ 32 370000?37ffff 1b8000?1bffff sa56 111000xxx 64/ 32 380000?38ffff 1c0000?1c7fff sa57 111001xxx 64/ 32 390000?39ffff 1c8000?1cffff sa58 111010xxx 64/32 3a0000?3 affff 1d0000?1d7fff sa59 111011xxx 64/32 3b0000?3 bffff 1d8000?1dffff sa60 111100xxx 64/32 3c0000?3 cffff 1e0000?1e7fff sa61 111101xxx 64/32 3d0000?3 dffff 1e8000?1effff sa62 111110xxx 64/32 3e0000?3 effff 1f0000?1f7fff sa63 111111000 8/4 3f0000?3f1fff 1f8000?1f8fff sa64 111111001 8/4 3f2000?3f3fff 1f9000?1f9fff sa65 111111010 8/4 3f4000?3f5fff 1fa000?1fafff sa66 111111011 8/4 3f6000?3f7fff 1fb000?1fbfff sa67 111111100 8/4 3f8000?3f9fff 1fc000?1fcfff sa68 111111101 8/4 3fa000?3fbfff 1fd000?1fdfff sa69 111111110 8/4 3fc000?3fdfff 1fe000?1fefff sa70 111111111 8/4 3fe000?3fffff 1ff000?1fffff note : the address bus is a20 : a-1 in byte mode where byte# = v b il b or a20 : a0 in word mode where byte# = v b ih b
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 7 en29lv320a rev. b, issue date: 2007 / 07 / 17 u table 2b. bottom boot sector address tables (en29lv320ab) sector a20 ? a12 sector size (kbytes / kwords) address range (h) byte mode (x8) address range (h) word mode (x16) sa0 000000000 8/4 000000?001fff 000000?000fff sa1 000000001 8/4 002000?003fff 001000?001fff sa2 000000010 8/4 004000?005fff 002000?002fff sa3 000000011 8/4 006000?007fff 003000?003fff sa4 000000100 8/4 008000?009fff 004000?004fff sa5 000000101 8/4 00a000?00bfff 005000?005fff sa6 000000110 8/4 00c000?00dfff 006000?006fff sa7 000000111 8/4 00e000?00ffff 007000?007fff sa8 000001xxx 64/32 010 000?01ffff 00 8000?00ffff sa9 000010xxx 64/32 020 000?02ffff 01 0000?017fff sa10 000011xxx 64/32 030000 ?03ffff 018000?01ffff sa11 000100xxx 64/32 040 000?04ffff 02 0000?027fff sa12 000101xxx 64/32 050000 ?05ffff 028000?02ffff sa13 000110xxx 64/32 060 000?06ffff 03 0000?037fff sa14 000111xxx 64/32 070000 ?07ffff 038000?03ffff sa15 001000xxx 64/32 080 000?08ffff 04 0000?047fff sa16 001001xxx 64/32 090000 ?09ffff 048000?04ffff sa17 001010xxx 64/32 0a0 000?0affff 050000?057fff sa18 001011xxx 64/32 0b0000 ?0bffff 058000?05ffff sa19 001100xxx 64/32 0c0 000?0cffff 060000?067fff sa20 001101xxx 64/32 0d0000 ?0dffff 068000?06ffff sa21 001110xxx 64/32 0e0 000?0effff 070000?077fff sa22 001111xxx 64/32 0f0000 ?0fffff 078000?07ffff sa23 010000xxx 64/32 100 000?10ffff 08 0000?087fff sa24 010001xxx 64/32 110000 ?11ffff 088000?08ffff sa25 010010xxx 64/32 120 000?12ffff 09 0000?097fff sa26 010011xxx 64/32 130000 ?13ffff 098000?09ffff sa27 010100xxx 64/32 140000 ?14ffff 0a0000?0a7fff sa28 010101xxx 64/32 150000 ?15ffff 0a8000?0affff sa29 010110xxx 64/32 160000 ?16ffff 0b0000?0b7fff sa30 010111xxx 64/32 170000 ?17ffff 0b8000?0bffff sa31 011000xxx 64/32 180000?18ffff 0c0000?0c7fff sa32 011001xxx 64/32 190000?19ffff 0c8000?0cffff sa33 011010xxx 64/32 1a0000?1affff 0d0000?0d7fff sa34 011011xxx 64/32 1b0000?1bffff 0d8000?0dffff sa35 011100xxx 64/32 1c0000?1cffff 0e0000?0e7fff sa36 011101xxx 64/32 1d0000 ?1dffff 0e8000?0effff sa37 011110xxx 64/32 1e0000?1effff 0f0000?0f7fff sa38 011111xxx 64/32 1f0000?1fffff 0f8000?0fffff
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 8 en29lv320a rev. b, issue date: 2007 / 07 / 17 sa39 100000xxx 64/32 200 000?20ffff 10 0000?107fff sa40 100001xxx 64/32 210000 ?21ffff 108000?10ffff sa41 100010xxx 64/32 220 000?22ffff 11 0000?117fff sa42 100011xxx 64/32 230000 ?23ffff 118000?11ffff sa43 100100xxx 64/32 240 000?24ffff 12 0000?127fff sa44 100101xxx 64/32 250000 ?25ffff 128000?12ffff sa45 100110xxx 64/32 260 000?26ffff 13 0000?137fff sa46 100111xxx 64/32 270000 ?27ffff 138000?13ffff sa47 101000xxx 64/32 280 000?28ffff 14 0000?147fff sa48 101001xxx 64/32 290000 ?29ffff 148000?14ffff sa49 101010xxx 64/32 2a0 000?2affff 150000?157fff sa50 101011xxx 64/32 2b0000 ?2bffff 158000?15ffff sa51 101100xxx 64/32 2c0 000?2cffff 160000?167fff sa52 101101xxx 64/32 2d0000 ?2dffff 168000?16ffff sa53 101110xxx 64/32 2e0 000?2effff 170000?177fff sa54 101111xxx 64/32 2f0000 ?2fffff 178000?17ffff sa55 110000xxx 64/32 300 000?30ffff 18 0000?187fff sa56 110001xxx 64/32 310000 ?31ffff 188000?18ffff sa57 110010xxx 64/32 320 000?32ffff 19 0000?197fff sa58 110011xxx 64/32 330000 ?33ffff 198000?19ffff sa59 110100xxx 64/32 340000 ?34ffff 1a0000?1a7fff sa60 110101xxx 64/32 350000 ?35ffff 1a8000?1affff sa61 110110xxx 64/32 360000 ?36ffff 1b0000?1b7fff sa62 110111xxx 64/32 370000 ?37ffff 1b8000?1bffff sa63 111000xxx 64/32 380000?38ffff 1c0000?1c7fff sa64 111001xxx 64/32 390000?39ffff 1c8000?1cffff sa65 111010xxx 64/32 3a0000?3affff 1d0000?1d7fff sa66 111011xxx 64/32 3b0000?3bffff 1d8000?1dffff sa67 111100xxx 64/32 3c0000 ?3cffff 1e0000?1e7fff sa68 111101xxx 64/32 3d0000 ?3dffff 1e8000?1effff sa69 111110xxx 64/32 3e0000?3effff 1f0000?1f7fff sa70 111111xxx 64/32 3f0000?3fffff 1f8000?1fffff note : the address bus is a20 : a-1 in byte mode where byte# = v b il b or a20 : a0 in word mode where byte# = v b ih b
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 9 en29lv320a rev. b, issue date: 2007 / 07 / 17 product selector guide product number en29lv320a speed option -70 -90 max access time, ns (t b acc b ) 70 90 max ce# access, ns (t b ce b ) 70 90 max oe# access, ns (t b oe b ) 30 35 notes: 1. vcc=3.0 ? 3.6 v for 70ns read operation block diagram we# ce# oe# state control command register erase voltage generator input/output buffers program voltage generator chip enable output enable logic data latch y-decoder x-decoder y-gating cell matrix timer vcc detector a0-a20 vcc vss dq0-dq15 (a-1) address latch block protect switches stb stb ry/by#
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 10 en29lv320a rev. b, issue date: 2007 / 07 / 17 table 3. operating modes 32m flash user mode table dq8-dq15 operation ce# oe# we# reset # wp#/ac c a0- a20 dq0- dq7 byte# = v b ih b byte# = v b il b read l l h h l/h a b in b d b out b d b out b write l h l h (note 1) a b in b d b in b d b in b accelerated program l h l h v b hh a b in b d b in b d b in b dq8- dq14= high-z, dq15 = a -1 cmos standby v b cc b 0.3v x x v b cc b 0.3v h x high-z high-z high-z ttl standby h x x h h x high-z high-z high-z output disable l h h h l/h x high-z high-z high-z hardware reset x x x l l/h x high-z high-z high-z sector (group) protect l h l v b id b l/h sa, a6=l, a1=h, a0=l (note 2) x x sector unprotect l h l v b id b (note 1) sa, a6=h, a1=h, a0=l (note 2) x x temporary sector unprotect x x x v b id b (note 1) a b in b (note 2) (note 2) high-z l=logic low= v b il b , h=logic high= v b ih b , v b id b =v b hh =11 0.5v = 10.5-11.5v, x=don?t care (e ither l or h, but not floating ), sa=sector addresses, d b in b =data in, d b out b =data out, a b in b =address in notes: 1. if wp#/acc = v b il b , the two outermost boot sectors remain protected. if wp# / acc = v b ih b , the outermost boot sector protection depends on whether they were last protected or unprotected. if wp#/acc = v b hh b , all sectors will be unprotected. 2. please refer to ?sector/sector group protection & chip unprotection?, flowchart 7a and flowchart 7b.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 11 en29lv320a rev. b, issue date: 2007 / 07 / 17 table 4. autoselect codes (using high voltage, v b id b ) 32m flash manufacturer/device id table l=logic low= v b il b , h=logic high= v b ih b , v b id b =11 0.5v, x=don?t care (either l or h, but not floating!), sa=sector addresses note: 1. a8=h is recommended for manufacturing id check. if a manufacturing id is read with a8=l, the chip will output a configuration code 7fh. 2. a9 = v b id b is for hv a9 autoselect mode only. a9 must be vcc (cmos logic level) for command autoselect mode. description ce# oe# we# a20 to a12 a11 to a10 a9 p 2 p a8 a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 h p 1 p 1ch manufacturer id: eon l l h x x v b id b l xlxll x 7fh word l l h 22h f6h device id (top boot sector) byte l l h x x v b id b xxlxlh x f6h word l l h 22h f9h device id (bottom boot sector) byte l l h x x v b id b xxlxlh x f9h x 01h (protected) sector protection verification l l h sa x v b id b xxlxhl x 00h (unprotected)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 12 en29lv320a rev. b, issue date: 2007 / 07 / 17 user mode definitions word / byte configuration the signal set on the byte# pin controls whether the device data i/o pins dq15-dq0 operate in the byte or word configuration. when the byte# pin is set at logic ?1?, then the device is in word configuration, dq15-dq0 are active and are controlled by ce# and oe#. on the other hand, if the byte# pin is set at logic ?0?, then the device is in byte configuration, and only data i/o pins dq0-dq7 are active and controlled by ce# and oe#. the data i/o pins dq8-dq14 are tri- stated, and the dq15 pin is used as an input for the lsb (a-1) address function. standby mode the en29lv320a has a cmos-compatible standby mode, which reduces the b current to < 1a (typical). it is placed in cmos-compatible standby when the ce# pin is at v b cc b 0.5. reset# and byte# pin must also be at cmos input levels. the device also has a ttl-compatible standby mode, which reduces the maximum v b cc b current to < 1ma. it is placed in ttl-compatible standby when the ce# pin is at v b ih b . when in standby modes, the outputs are in a high-impedance state independent of the oe# input. automatic sleep mode the en29lv320a has a auto matic sleep mode, which minimizes po wer consumption. the devices will enter this mode automatically when the states of address bus remain stable for t acc + 30ns. icc 4 in the dc characteristics table shows the current specification. with standard access times, the device will output new data when addresses change. read mode the device is automatically set to reading array data after device power-up or hardware reset. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm after the device accepts an sector erase suspend command, the device enters the sector erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the sector erase suspend mode, the system may once again read array data with the same exception. see ?sector erase suspend/resume commands? for more additional information. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high or while in the autoselect mode. see the ?reset command? for additional details. output disable mode when the oe# pin is at a logic high level (v b ih b ), the output from the en29lv320a is disabled. the output pins are placed in a high impedance state. autoselect identification mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq15?dq0. this mode is primarily inte nded for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v b id b (10.5 v to 11.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in autoselect codes table. in addition, when verifying
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 13 en29lv320a rev. b, issue date: 2007 / 07 / 17 sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the ?command definitions? table shows the remaining address bits that are don?t-care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15?dq0. to access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v b id b . see ?command definitions? for details on using the autoselect mode. writing command sequences to write a command or command sequence to program data to the device or erase data, the system has to drive we# and ce# to v b il , and oe# to v b ih b . for program operations, the byte# pin determines whether the device accepts program data in bytes or words. an erase operation can erase one sector or the whole chip. the system can also read the autoselect codes by entering the autoselect mode, which need the autoselect command sequence to be written. please refer to the ?command definitions? for all the available commands. reset#: hardware reset when reset# is driven low for t b rp b , all output pins are tristates. all commands written in the internal state machine are reset to reading array data. please refer to timing diagram for reset# pin in ?ac characteristics?. sector/sector group protect ion & chip unprotection the hardware sector group protection feature disables both program and erase operations in any sector. the hardware chip unprotection feature re-enables both program and erase operations in previously protected sectors. a sector group implies three or four adjacent sectors that would be protected at the same time. please see the following tables which show the organization of sector groups. there are two methods to enable this hardware protection circuitry. the first one requires only that the reset# pin be at v id and then standard microprocessor timings can be used to enable or disable this feature. see flowchart 7a and 7b for the algorithm and figure. 12 for the timings. when doing chip unprotect, all the unprotected sector groups must be protected prior to any unprotect write cycle. the second method is for programming equipment. this method requires v id to be applied to both oe# and a9 pins and non-standard microprocessor timings are used. this method is described in a separate document named en29lv320a supplement, which can be obtained by contacting a representative of eon silicon solution, inc. u
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 14 en29lv320a rev. b, issue date: 2007 / 07 / 17 top boot sector/sector group organization table (en29lv320at) for (un)protection sector group sectors a20-a12 sector group size sg 0 sa 0-sa 3 0000xxxxx 64 kbytes x 4 sg 1 sa 4-sa 7 0001xxxxx 64 kbytes x 4 sg 2 sa 8-sa11 0010xxxxx 64 kbytes x 4 sg 3 sa12-sa15 0011xxxxx 64 kbytes x 4 sg 4 sa16-sa19 0100xxxxx 64 kbytes x 4 sg 5 sa20-sa23 0101xxxxx 64 kbytes x 4 sg 6 sa24-sa27 0110xxxxx 64 kbytes x 4 sg 7 sa28-sa31 0111xxxxx 64 kbytes x 4 sg 8 sa32-sa35 1000xxxxx 64 kbytes x 4 sg 9 sa36-sa39 1001xxxxx 64 kbytes x 4 sg10 sa40-sa43 1010xxxxx 64 kbytes x 4 sg11 sa44-sa47 1011xxxxx 64 kbytes x 4 sg12 sa48-sa51 1100xxxxx 64 kbytes x 4 sg13 sa52-sa55 1101xxxxx 64 kbytes x 4 sg14 sa56-sa59 1110xxxxx 64 kbytes x 4 sg15 sa60-sa62 111100xxx 111101xxx 111110xxx 64 kbytes x 3 sg16 sa63 111111000 8 kbytes sg17 sa64 111111001 8 kbytes sg18 sa65 111111010 8 kbytes sg19 sa66 111111011 8 kbytes sg20 sa67 111111100 8 kbytes sg21 sa68 111111101 8 kbytes sg22 sa69 111111110 8 kbytes sg23 sa70 111111111 8 kbytes bottom boot sector/sector group organizati on table (en29lv320ab) for (un)protection sector group sectors a20-a12 sector group size sg23 sa70-sa67 1111xxxxx 64 kbytes x 4 sg22 sa66-sa63 1110xxxxx 64 kbytes x 4 sg21 sa62-sa59 1101xxxxx 64 kbytes x 4 sg20 sa58-sa55 1100xxxxx 64 kbytes x 4 sg19 sa54-sa51 1011xxxxx 64 kbytes x 4 sg18 sa50-sa47 1010xxxxx 64 kbytes x 4 sg17 sa46-sa43 1001xxxxx 64 kbytes x 4 sg16 sa42-sa39 1000xxxxx 64 kbytes x 4 sg15 sa38-sa35 0111xxxxx 64 kbytes x 4 sg14 sa34-sa31 0110xxxxx 64 kbytes x 4 sg13 sa30-sa27 0101xxxxx 64 kbytes x 4 sg12 sa26-sa23 0100xxxxx 64 kbytes x 4 sg11 sa22-sa19 0011xxxxx 64 kbytes x 4 sg10 sa18-sa15 0010xxxxx 64 kbytes x 4 sg 9 sa14-sa11 0001xxxxx 64 kbytes x 4 sg 8 sa10-sa 8 000011xxx 000010xxx 000001xxx 64 kbytes x 3 sg 7 sa 7 000000111 8 kbytes sg 6 sa 6 000000110 8 kbytes sg 5 sa 5 000000101 8 kbytes sg 4 sa 4 000000100 8 kbytes sg 3 sa 3 000000011 8 kbytes sg 2 sa 2 000000010 8 kbytes sg 1 sa 1 000000001 8 kbytes sg 0 sa 0 000000000 8 kbytes
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 15 en29lv320a rev. b, issue date: 2007 / 07 / 17 write protect / accelerated program (wp# / acc) the wp#/acc pin provides two functions. the write protect (wp#) function provides a hardware method of protecting the outermost two 8k-byte boot sector. the acc function allows faster manufacturing throughput at the factory, using an external high voltage. when wp#/acc is low, the device protects the outermost tw 8k-byte boot sector; no matter the sectors are protected or unprotected using the method described in ?sector/sector group protection & chip unprotection?, program and erase operations in these sectors are ignored. when wp#/acc is high, the device reverts to the previous protection status of the outermost two 8k-byte boot sector. program and erase operations can now modify the data in the two outermost 8k-byte boot sector unless the sector is protected using sector protection. when wp#/acc is raised to v hh the memory automatically enters the unlock bypass mode(please refer to ?command definitions?), tempor arily unprotects every protected sect ors, and reduces the time required for program operation. the system would use a two-cycle program command sequence as required by the unlock bypass mode. when wp#/acc returns to v ih or v il , normal operation resumes. the transitions from v ih or v il to v hh and from v hh to v ih or v il must be slower than t b vhh b , see figure 11. note that the wp#/acc pin must not be left floating or unconnected. in addition, wp#/acc pin must not be at v hh for operations other than accelerated programming. it could cause the device to be damaged. never raise this pin to v hh from any mode except read mode, otherwise the memory may be left in an indeterminate state. a 0.1f capacitor should be connected between the wp#/acc pin and the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during unlock bypass program. temporary sector unprotect this feature allows temporary unprotection of previously protected sector groups to change data while in-system. the temporary sector unprotect mode is activated by setting the reset# pin to vbidb. during this mode, formerly protected sectors can be programmed or erased by simply selecting the sector addresses. once vbidb is removed from the reset# pin, all the previously protected sectors are protected again. see accompanying flowchart and figure 10 for more timing details. common flash interface (cfi) the common flash interface (cfi) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-independent, jedec id- independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. start reset#=v b id b b (note 1) b perform erase or program operations reset#=v b ih b temporary sector unprotect com p leted b ( note 2 ) notes: 1. all protected sectors are unprotected. (if wp#/acc=v b il b , outermost boot sectors will remain protected.) 2. previousl y p rotected sectors are p rotected a g ain.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 16 en29lv320a rev. b, issue date: 2007 / 07 / 17 this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 5-8.in word mode, the upper address bits (a7?msb) must be all zeros. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode and the system can read cfi data at the addresses given in tables 5?8. the system must write the reset command to return the device to the autoselect mode. table 5. cfi query identification string addresses (word mode) adresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) table 6. system interface string addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h vcc min (write/erase) dq7-dq4: volt, dq3 ?dq0: 100 millivolt 1ch 38h 0036h vcc max (write/erase) dq7-dq4: volt, dq3 ?dq0: 100 millivolt 1dh 3ah 0000h vpp min. voltage (00h = no vpp pin present) 1eh 3ch 0000h vpp max. voltage (00h = no vpp pin present) 1fh 3eh 0004h typical timeout per single byte/word write 2 p n p s 20h 40h 0000h typical timeout for min, size buffer write 2 p n p s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 p n p ms 22h 44h 0000h typical timeout for full chip erase 2 p n p ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 p n p times typical 24h 48h 0000h max. timeout for buffer write 2 p n p times typical 25h 4ah 0004h max. timeout per individual block erase 2 p n p times typical 26h 4ch 0000h max timeout for full chip erase 2 p n p times typical (00h = not supported) table 7. device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0016h device size = 2 p n p bytes 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 17 en29lv320a rev. b, issue date: 2007 / 07 / 17 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2 p n p (00h = not supported) 2ch 58h 0002h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification of cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 003eh 0000h 0000h 0001h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information table 8. primary vendor-specific extended query addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0031h minor version number, ascii 45h 8ah 0000h address sensitive unlock 0 = required, 1 = not required 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0004h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 01 = 29f040 mode, 02 = 29f016 mode, 03 = 29f400 mode, 04 = 29lv800a mode 4ah 94h 0000h simultaneous operation 00 = not supported, 01 = supported 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00a5h minimum acc (acceleration) supply voltage 00 = not supported, dq7-dq4 : volts, dq3-dq0 : 100mv 4eh 9ch 00b5h maximum acc (acceleration) supply voltage 00 = not supported, dq7-dq4 : volts, dq3-dq0 : 100mv 4fh 9eh 0002h/ 0003h top/bottom boot sector identifier 02h = bottom boot, 03h = top boot
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 18 en29lv320a rev. b, issue date: 2007 / 07 / 17 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the command definitions table. additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during vcc power up and power down transitions, or from system noise. low v b cc b write inhibit when vcc is less than v b lko b , the device does not accept any write cycles. this protects data during vcc power up and power down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until vcc is greater than v b lko b . the system must provide the proper signals to the control pins to prevent unintentional writes when vcc is greater than v b lko b . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v b il b , ce# = v b ih b , or we# = v b ih b . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. if ce#, we#, and oe# are all logical zero (not recommended usage), it w ill be considered a read. power-up write inhibit during power-up, the device automatically resets to read mode and locks out write cycles. even with ce# = v b il b , we#= v b il b and oe# = v b ih b , the device will not accept co mmands on the rising edge of we#.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 19 en29lv320a rev. b, issue date: 2007 / 07 / 17 command definitions the operations of the device are selected by one or more commands written into the command register. commands are made up of data sequences written at specific addresses via the command register. the sequences for the specified operation are defined in the command definitions table (table 9). incorrect addresses, incorrect data values or improper sequences will reset the device to read mode. table 9. en29lv320a command definitions bus cycles 1 p st p cycle 2 p nd p cycle 3 p rd p cycle 4 p th p cycle 5 p th p cycle 6 p th p cycle command sequence cycles addr data addr data addr data addr data addr data addr data read 1 ra rd reset 1 xxx f0 000 7f word 555 2aa 555 100 1c 000 7f manufacturer id byte 4 aaa aa 555 55 aaa 90 200 1c word 555 2aa 555 x01 22f6 device id top boot byte 4 aaa aa 555 55 aaa 90 x02 f6 word 555 2aa 555 x01 22f9 device id bottom boot byte 4 aaa aa 555 55 aaa 90 x02 f9 00 word 555 2aa 555 (sa) x02 01 00 autoselect sector protect verify byte 4 aaa aa 555 55 aaa 90 (sa) x04 01 word 555 2aa 555 program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 unlock bypass byte 3 aaa aa 555 55 aaa 20 unlock bypass program 2 xxx a0 pa pd unlock bypass reset 2 xxx 90 xxx 00 word 555 2aa 555 555 2aa 555 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 sector erase suspend 1 xxx b0 sector erase resume 1 xxx 30 word 55 cfi query byte 1 aa 98 address and data values indicated are in hex. unless specified, all bus cycles are write cycles ra = read address: address of the memory location to be read. this is a read cycle. rd = read data: data read from location ra during read operation. this is a read cycle. pa = program address: address of the memory location to be programmed. x = don?t-care pd = program data: data to be programmed at location pa sa = sector address: address of the sector to be erased or verified. address bits a20-a12 uniquely select any sector.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 20 en29lv320a rev. b, issue date: 2007 / 07 / 17 reading array data the device is automatically set to reading array data after power up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. following a sector erase suspend command, sector erase suspend mode is entered. the system can read array data using the standard read timings from sectors other than the one which is being erase-suspended. if the system reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the sector erase suspend mode, the system may once again read array data with the same exception. the reset command must be issued to re-enable the device for reading array data if dq5 goes high during an active program or erase operation or while in the autoselect mode. see next section for details on reset. reset command writing the reset command to the device resets the device to reading array data. address bits are don?t-care for this command. the reset command may be written between the cycle sequences in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in sector erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the cycle sequences in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data. if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies in sector erase suspend mode). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices id codes, and determine whether or not a sector (group) is protected. the command definitions table shows the address and data requirements. this is an alternative to the method that requires v b id b on address bit a9 and is intended for commercial programmers. two unlock cycles followed by the autoselect command initiate the autoselect command sequence. autoselect mode is then entered and the system may read at addresses shown in table 9 any number of times, without needing another command sequence. the system must write the reset command to exit the autoselect mode and return to reading array data. word / byte programming command the device can be programmed by byte or by word, depending on the state of the byte# pin. programming the en29lv320a is performed by using a four-bus-cycle operation (two unlock write cycles followed by the program setup command and program data write cycle). when the program command is executed, no additional cpu controls or timings are necessary. an internal timer terminates the program operation automatically. address is latched on the falling edge of ce# or we#, whichever is last; data is latched on the rising edge of ce# or we#, whichever is first.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 21 en29lv320a rev. b, issue date: 2007 / 07 / 17 any commands written to the device during the program operation are ignored. programming status can be checked by sampling data on dq7 (dat a# polling) or on dq6 (t oggle bit). when the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. note that data can not be programmed from a ?0? to a ?1?. attempting to do so may halt the operation and set dq5 to ?1?, or cause the data# polling algorithm to indicate the operation was su ccessful. however, a succ eeding read will show that the data is still ?0?. only erase operations ca n convert a ?0? to a ?1?. when programming time limit is exceeded, dq5 w ill produce a logical ?1? and a reset command can return the device to read mode. programming is allowed in any sequence across sector boundaries. unlock bypass to speed up programming operation, the unlock bypass command may be used. once this feature is activated, the shorter two-cycle unlock bypass program command can be used instead of the normal four-cycle program command to program the device. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset command can be accepted. this mode is exited after issuing the unlock bypass reset command. the device powers up with this feature disabled the device provides accelerated program operations through the wp#/acc pin. when wp#/acc is asserted to v b hh b , the device automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. chip erase command chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded chip erase algorithm are ignored. the system can determine the status of the erase operation by using dq7, dq6, or dq2. see ?write operation status? for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. once the sector erase operation has begun, only the sector erase suspend command is valid. all other commands are ignored. if there are several sectors to be erased, sector erase command sequences must be issued for each sector. that is, only a sector address can be specified for each sector erase command . users must issue another sector erase command for the next sector to be erased after the previous one is completed.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 22 en29lv320a rev. b, issue date: 2007 / 07 / 17 when the embedded erase algorithm is completed, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to ?write operation status? for information on these status bits. flowchart 4 illustrates the algorithm for the erase op eration. refer to the er ase/program operations tables in the ?ac characteristics? section for parameters, and to the sector erase operations timing diagram for timing waveforms. sector erase suspend / resume command the sector erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation. the sector erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. addresses are don?t-cares when writing the sector erase suspend command. when the sector erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. normal read and write timings and command definitions apply. please note that autoselect command sequence can not be accepted during sector erase suspend . reading at any address within erase-suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see ?write operation status? for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the autoselect command is not supported during sector erase suspend mode. the system must write the sector erase resume command (address bits are don?t-care) to exit the sector erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another sector erase suspend command can be written after the device has resumed erasing. write operation status dq7: data# polling the en29lv320a provides data# polling on dq7 to indicate the status of the embedded operations. the data# polling feature is active during the word/byte programming, sector erase, chip erase, and sector erase suspend. (see table 10) when the embedded programming is in progress, an attemp t to read the device will produce the complement of the data written to dq7. upon the completion of the programming operation, an attempt to read the device will pr oduce the true data written to dq7. data# polling is valid after the rising edge of the fourth we# or ce# pulse in the four-cycle sequence for program. when the embedded erase is in progress, an attemp t to read the device will produce a ?0? at the dq7 output. upon the completion of the embedded erase, the device will produce the ?1? at the dq7 output during the read cycl es. for chip erase or sector erase, data# polling is valid after the rising edge of the last we# or ce# pulse in the six-cycle sequence.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 23 en29lv320a rev. b, issue date: 2007 / 07 / 17 data# polling must be performed at any address within a sector that is being programmed or erased and not a protected sector. otherwise, data # polling may give an ina ccurate result if the address used is in a protected sector. just prior to the completion of the embedded operations, dq7 may change asynchronously when the output enable (oe#) is low. this means that the device is driving status information on dq7 at one instant of time and valid data at the next instant of time. depending on the time the system samples the dq7 output, it may read the status of valid data. even if the device has completed the embedded operation and dq 7 has a valid data, the data output on dq0-dq 6 may be still invalid. the valid data on dq0-dq7 should be read on the subsequent read attempts. the flowchart for data# polling (d q7) is shown on flowchart 5. the data# polling (dq7) timing diagram is shown in figure 6. ry/by#: ready/busy status output the ry/by# is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or completed. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to vcc. in the output-low period, signifying busy, the device is actively erasing or programming. this includes programming in the erase suspend mode. if the output is high, signifying the ready, the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. dq6: toggle bit i the en29lv320a provides a ?toggle bit? on dq6 to indicate the status of the embedded programming and erase operations. (see table 10) during an embedded program or erase operation, successive attempts to read data from the device at any address (by active oe# or ce#) will result in dq6 toggling between ?zero? and ?one?. once the embedded program or erase op eration is completed, dq6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit is valid after the rising edge of the fourth we# pulse in the four-cycle sequence. during erase operation, the toggle bit is valid after the rising edge of the sixth we# pulse for sector erase or chip erase. in embedded progra mming, if the sector being written to is protected, dq6 will toggles for about 2 s, then stop toggling without the data in the sector having changed. in sector erase or chip erase, if all selected sectors are protected, dq6 will toggle for about 100 s. the chip will then return to the read mode without changing data in all protected sectors. the flowchart for the toggle bit (dq6) is shown in flowchart 6. the toggle bit timing diagram is shown in figure 7 . dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed. since it is possible that dq5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the dq6 is toggling after detecting a ?1? on dq5. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has exceeded the timing limits,
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 24 en29lv320a rev. b, issue date: 2007 / 07 / 17 dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the output on dq3 can be checked to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) when sector erase starts, dq3 switches from ?0? to ?1?. this device does not support multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since it immediately shows as a ?1? after the first 30h command. future devices may support this feature. dq2: erase toggle bit ii the ?toggle bit? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase- suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to the following table to compare outputs for dq2 and dq6. flowchart 6 shows the toggle bit algorithm, and the section ?dq2: toggle bit? explains the algorithm. see also the ?dq6: toggle bit i? subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to flowchart 6 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, after the initial two read cycles, the system determines that the toggle bit is still toggling. and the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operat ion. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 25 en29lv320a rev. b, issue date: 2007 / 07 / 17 write operation status operation dq7 dq6 dq5 dq3 dq2 ry/by# embedded program algorithm dq7# toggle 0 n/a no toggle 0 standard mode embedded erase algorithm 0 toggle 0 1 toggle 0 reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase suspend mode erase-suspend program dq7# toggle 0 n/a n/a 0 table 10. status register bits dq name logic level definition ?1? erase complete or erased sector in sector erase suspend ?0? erase on-going dq7 program complete or data of non-erased sector during sector erase suspend 7 data# polling dq7# program on-going ?-1-0-1-0-1-0-1-? erase or program on-going dq6 read during sector erase suspend 6 toggle bit ?-1-1-1-1-1-1-1-? erase complete ?1? program or erase error 5 error bit ?0? program or erase on-going ?1? erase operation start 3 sector erase time bit ?0? erase timeout period on-going ?-1-0-1-0-1-0-1-? chip erase, sector erase or read within erase- suspended sector. (when dq5=1, erase error due to currently addressed sector or program on erase-suspended sector 2 toggle bit dq2 read on addresses of non erase-suspend sectors notes: dq7: data# polling: indicates the p/e status check during prog ram or erase, and on completion before checking bits dq5 for program or erase success. dq6: toggle bit: remains at constant level when p/e operati ons are complete or erase suspend is acknowledged. successive reads output complementary data on dq6 while programming or erase operation are on-going. dq5: error bit: set to ?1? if failure in programming or erase dq3: sector erase command timeout bit: operation has started. only possible command is erase suspend (es). dq2: toggle bit: indicates the erase status and allows identification of the erased sector.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 26 en29lv320a rev. b, issue date: 2007 / 07 / 17 embedded algorithms flowchart 1. embedded program start write program command sequence (shown below) data# poll device last address? programming done increment address no yes verify data? flowchart 2. embedded program command sequence (see the command definitions se ction for more information.) 2aah / 55h 555h / aah 555h / a0h program address / program data
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 27 en29lv320a rev. b, issue date: 2007 / 07 / 17 flowchart 3. embedded erase flowchart 4. embedded erase command sequence (see the command definitions se ction for more information.) chip erase sector erase 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 555h/aah 2aah/55h 555h/80h 555h/aah 2aah/55h sector address/30h start write erase command sequence data poll from system or toggle bit successfully completed erase done data =ffh? yes no
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 28 en29lv320a rev. b, issue date: 2007 / 07 / 17 flowchart 5. data# polling algorithm notes: (1) this second read is necessary in case the first read was done at the exact instant when the status data was in transition. flowchart 6. toggle bit algorithm notes: (2) this second set of reads is necessary in case the first set of reads was done at the exact instant when the status data was in transition. no yes dq6 = toggle? dq5 = 1? dq6 = toggle? no no yes yes read data twice start read data twice (2) fail pass no no dq7 = data? dq5 = 1? dq7 = data? yes yes no yes read data start read data (1) fail pass
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 29 en29lv320a rev. b, issue date: 2007 / 07 / 17 flowchart 7a. in-system sector (group) protect flowchart start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? no temporary chip unprotect mode yes set up sector (group) address to protect: write 60h to sector addr with a6 = 0, a1 = 1, a0 = 0 wait 150 s to verify: write 40h to sector(group) address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 data = 01h? no plscnt = 25? increment plscnt no device failed yes protect another sector? y es reset plscnt = 1 no remove v id from reset# write reset command sector protect complete sector protect algorithm yes wait 0.4 s
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 30 en29lv320a rev. b, issue date: 2007 / 07 / 17 flowchart 7b. in-system chip unprotect flowchart start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? temporary chip unprotect mode no yes all sectors protected? yes no protect all sectors (groups): the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address (see diagram 7a.) set up first sector address chip unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 wait 15 ms verify chip unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 =0 read from sector address with a6 = 1, a1 = 1, a0 = 0 data = 00h? no plsccnt = 1000? no increment plscnt yes device failed last sector verified? no set up next sector (group) address remove v id from reset# write reset command chip unprotect com p lete chip unprotect algorithm wait 0.4 s yes yes
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 31 en29lv320a rev. b, issue date: 2007 / 07 / 17 absolute maximum ratings parameter value unit storage temperature -65 to +125 c plastic packages -65 to +125 c ambient temperature with power applied -55 to +125 c output short circuit current p 1 p 200 ma a9, oe#, reset# p p and wp#/acc p 2 p -0.5 to +11.5 v all other pins p 3 p -0.5 to vcc+0.5 v voltage with respect to ground vcc -0.5 to + 4.0 v notes: 1. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. 2. minimum dc input voltage on a9, oe#, reset# and wp#/acc pins is ?0.5v. during voltage transitions, a9, oe#, reset# and wp#/acc pins may undershoot v b ss b to ?1.0v for periods of up to 50ns and to ?2.0v for periods of up to 20ns. see figure below. maximum dc input voltage on a9, oe#, and reset# is 11.5v which may overshoot to 12.5v for periods up to 20ns. 3. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, inputs may undershoot v b ss b to ?1.0v for periods of up to 50ns and to ?2.0 v for periods of up to 20ns. see figure below. maximum dc voltage on output and i/o pins is v b cc b + 0.5 v. during voltage transitions, outputs may overshoot to v b cc b + 1.5 v for periods up to 20ns. see figure below. 4. stresses above the values so mentioned above may cause permanent damage to the device. these values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. recommended operating ranges p 1 p parameter value unit ambient operating temperature commercial devices industrial devices 0 to 70 -40 to 85 c operating supply voltage vcc full voltage range: 2.7 to 3.6v v 1. recommended operating ranges define those limits between which the functionality of the device is guaranteed. vcc +1.5v maximum negative overshoot maximum positive overshoot waveform waveform
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 32 en29lv320a rev. b, issue date: 2007 / 07 / 17 dc characteristics table 11. dc characteristics (t b a b = 0c to 70c or - 40c to 85c; v b cc b = 2.7-3.6v) notes: 1. byte# pin can also be gnd 0.3v. byte# and reset# pin input buffers are always enabled so that they draw power if not at full cmos supply voltages. 2. maximum i b cc b specifications are tested with vcc = vcc max. symbol parameter test conditions min typ max unit i b li b input leakage current 0v v b in b vcc 5 a i b lo b output leakage current 0v v b out b vcc 5 a active read current ( byte mode ) 9 16 ma i b cc1 b active read current ( word mode ) ce# = v b il b ; oe# = v b ih ; b f = 5mhz 9 16 ma i b cc2 b supply current (program or erase) ce# = v b il b , oe# = v b ih b , we# = v b il b 20 30 ma i b cc3 b supply current (standby - cmos) ce# = byte# = reset# = vcc 0.3v (note 1) 1 5.0 a i b cc4 b reset current reset# = vss 0.3v 1 5.0 a i b cc5 b automatic sleep mode v b ih b = vcc 0.3v v b il b = vss 0.3v 1 5.0 ua v b il b input low voltage -0.5 0.8 v v b ih b input high voltage 0.7 x vcc vcc 0.3 v v b hh b #wp/acc voltage (write protect / program acceleration) 10.5 11.5 v v b id b voltage for autoselect or temporary sector unprotect 10.5 11.5 v v b ol b output low voltage i b ol b = 4.0 ma 0.45 v output high voltage ttl i b oh b = -2.0 ma 0.85 x vcc v v b oh b output high voltage cmos i b oh b = -100 a, vcc - 0.4v v v b lko b supply voltage (erase and program lock-out) 2.3 2.5 v
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 33 en29lv320a rev. b, issue date: 2007 / 07 / 17 test conditions test specifications notes: 1. vcc=3.0 ? 3.6 v for 70ns read operation test conditions -70 -90 unit output load 1 ttl gate output load capacitance, c b l b 30 100 pf input rise and fall times 5 5 ns input pulse levels 0.0-3.0 0.0-3.0 v input timing measurement reference levels 1.5 1.5 v output timing measurement reference levels 1.5 1.5 v device under test c l 6.2 k 2.7 k 3.3 v note: diodes are in3064 or equivalent
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 34 en29lv320a rev. b, issue date: 2007 / 07 / 17 ac characteristics hardware reset (reset#) speed options unit parameter std description test setup -70 -90 t ready reset# pin low to read or write embedded algorithms max 20 s t ready reset# pin low to read or write non embedded algorithms max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read min 50 ns t rpd reset# to standby mode min 20 s figure 1. ac waveforms for reset# reset# timings t rh t rp t ready 0 v ry/by# ce# oe# reset# reset timings not during automatic algorithms t ready t rh t rp ry/by# ce# oe# reset# reset timings during automatic algorithms
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 35 en29lv320a rev. b, issue date: 2007 / 07 / 17 ac characteristics word / byte configuration (byte#) speed unit std parameter description -70 -90 t b bcs b byte# to ce# switching setup time min 0 0 ns t b cbh b ce# to byte# switching hold time min 0 0 ns t b rbh b ry/by# to byte# switching hold time min 0 0 ns figure 2. ac waveforms for byte# byte# timings for read operations byte #timings for write operations note: switching byte# pin not allowed during embedded operations t bcs ce# oe# byte# ce# we# t cbh t bcs byte# t rbh ry/by#
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 36 en29lv320a rev. b, issue date: 2007 / 07 / 17 ac characteristics table 12. read-only operations characteristics parameter symbols speed options jedec standard description test setup -70 -90 unit t b avav b t b rc b read cycle time min 70 90 ns t b avqv b t b acc b address to output delay ce# = v b il oe# b b = b b v b il b max 70 90 ns t b elqv b t b ce b chip enable to output delay oe# b b = v b il b max 70 90 ns t b glqv b t b oe b output enable to output delay max 30 35 ns t b ehqz b t b df b chip enable to output high z max 20 20 ns t b ghqz b t b df b output enable to output high z max 20 20 ns t b axqx b t b oh b output hold time from addresses, ce# or oe#, whichever occurs first min 0 0 ns read min 0 0 ns t b oeh b output enable hold time toggle and data# polling min 10 10 ns notes: for - 70 vcc = 3.0v ? 3.6v output load: 1 ttl gate and 30pf input rise and fall times: 5ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level, input and output: 1.5 v - 90 vcc = 2.7v ? 3.6v output load: 1 ttl gate and 100 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level, input and output: 1.5 v figure 3. ac waveforms for read operations addresses ce# oe# we# outputs reset# ry/by# 0v output valid t b rc b t b acc t b oe b t b ce b t b oeh b t b oh t b df high z addresses stable
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 37 en29lv320a rev. b, issue date: 2007 / 07 / 17 ac characteristics table 13. write (erase/program) operations parameter symbols speed options jedec standard description -70 -90 unit t b avav b t b wc b write cycle time min 70 90 ns t b avwl b t b as b address setup time min 0 0 ns t b wlax b t b ah b address hold time min 45 45 ns t b dvwh b t b ds b data setup time min 30 45 ns t b whdx b t b dh b data hold time min 0 0 ns t b oes b output enable setup time min 0 0 ns read min 0 0 ns t b oeh b output enable hold time toggle and data# polling min 10 10 ns t b ghwl b t b ghwl b read recovery time before write (oe# high to we# low) min 0 0 ns t b elwl b t b cs b ce# setup time min 0 0 ns t b wheh b t b ch b ce# hold time min 0 0 ns t b wlwh b t b wp b write pulse width min 45 45 ns t b whdl b t b wph b write pulse width high min 20 20 ns byte typ 8 8 t b whw1 b t b whwh1 b programming operation word typ 8 8 s t b whw1 b t b whwh1 b accelerated programming operation (word and byte mode) typ 7 7 s t b whw2 b t b whwh2 b sector erase operation typ 0.5 0.5 s t b whw3 b t b whwh3 b chip erase operation typ 70 70 s t b vcs b vcc setup time min 50 50 s
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 38 en29lv320a rev. b, issue date: 2007 / 07 / 17 ac characteristics table 14. write (erase/program) operations alternate ce# controlled writes parameter symbols speed options jedec standard description -70 -90 unit t b avav b t b wc b write cycle time min 70 90 ns t b avel b t b as b address setup time min 0 0 ns t b elax b t b ah b address hold time min 45 45 ns t b dveh b t b ds b data setup time min 30 45 ns t b ehdx b t b dh b data hold time min 0 0 ns t b oes b output enable setup time min 0 0 ns t b ghel b t b ghel b read recovery time before write (oe# high to ce# low) min 0 0 ns t b wlel b t b ws b we# setup time min 0 0 ns t b ehwh b t b wh b we# hold time min 0 0 ns t b eleh b t b cp b ce# pulse width min 35 45 ns t b ehel b t b cph b ce# pulse width high min 20 20 ns byte typ 8 8 t b whw1 b t b whwh1 b programming operation word typ 8 8 s t b whw1 b t b whwh1 b accelerated programming operation (word and byte mode) typ 7 7 s t b whw2 b t b whwh2 b sector erase operation typ 0.5 0.5 s
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 39 en29lv320a rev. b, issue date: 2007 / 07 / 17 ac characteristics figure 4. ac waveforms for chip/sector erase operations timings notes: 1. sa=sector address (for sector erase) , va=valid address for reading status, d b out b =true data at read address. 2. v b cc b shown only to illustrate t b vcs b measurement references. it cannot o ccur as shown during a valid command sequence. t dh t ds t busy t wph t ch t wp t cs t vcs t rb t wc t as t ah t ghw l t whwh2 or t whwh3 0x2aa sa va va 0x55 0x30 status d out addresses ce# oe# we# data ry/by# v cc 0x555 for chip erase erase command sequence (last 2 cycles) read status data (last two cycles)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 40 en29lv320a rev. b, issue date: 2007 / 07 / 17 figure 5. program operation timings notes: 1. pa=program address, pd=program data, d b out b is the true data at the program address. 2. v b cc b shown in order to illustrate t b vcs b measurement references. it cannot occur as shown during a valid command sequence. t vcs t dh t rb t whwh1 t busy t ds t cs t wph t ch t wp t ghwl t wc t as t ah 0x555 pa pa pa pd status d out oxa0 addresses ce# oe# we# data ry/by# v cc program command sequence (last 2 cycles) program command sequence (last 2 cycles)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 41 en29lv320a rev. b, issue date: 2007 / 07 / 17 figure 6. ac waveforms for /data po lling during embedded algorithm operations notes: 1. va=valid address for reading data# polling status data 2. this diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cy cle. figure 7. ac waveforms for toggle bit during embedded algorithm operations t oeh t df t oh t bus t oe complement status data comple- ment true true status data valid data valid data t ce t acc t ch t rc va va va addresses ce# oe# we# dq[7] dq[6:0] ry/by# t rc t acc t ce t oe t oeh t ch t df t oh t busy va va va va valid status valid status valid status valid data (first read) (second d) (stops toggling) addresses ce# oe# we# dq6, dq2 ry/by#
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 42 en29lv320a rev. b, issue date: 2007 / 07 / 17 figure 8. alternate ce# controlled write operation timings notes: pa = address of the memory location to be programmed. pd = data to be programmed at byte address. va = valid address for reading program or erase status d b out b = array data read at va shown above are the last two cycles of the program or erase command sequence and the last status read cycle resett# shown to illustrate t b rh b measurement references. it cannot occur as shown during a valid command sequence. figure 9. dq2 vs. dq6 t wc t rh t as t ah t wh t ghel t cph t cp t ws t dh t ds t busy t cwhwh1 / t cwhwh2 / t cwhwh3 status d out 0xa0 for program pd for program 0x30 for sector erase 0x10 for chip erase va addresses we# oe# ce# data ry/by# reset# pa for program sa for sector erase 0x555 for chip erase 0x555 for program 0x2aa for erase we# dq6 dq2 enter embedded erase erase suspend enter erase suspend program erase resume erase enter suspend read enter suspend program erase erase complete erase suspend read
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 43 en29lv320a rev. b, issue date: 2007 / 07 / 17 ac characteristics temporary sector unprotect speed option unit parameter std description -70 -90 t b vidr b v b id b rise and fall time min 500 ns t b vihh b v b hh b rise and fall time min 500 ns t b rsp b reset# setup time for temporary sector unprotect min 4 s figure 10. temporary sector unprotect timing diagram ac characteristics write protect / accelerated program figure 11. accelerated program timing diagram 0 or 3 v wp#/acc t b vhh b t b vhh b t b rsp b v b hh b 0 or 3 v ce# we# 0 or 3 v reset# t vidr t vidr t rsp v id 0 or 3 v ce# we# ry/by#
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 44 en29lv320a rev. b, issue date: 2007 / 07 / 17 ac characteristics sector (group) protec t and chip unprotect figure 12. sector (group) protect and chip unprotect timing diagram notes: use standard microprocessor timings for this device for read and write cycles. for sector (group) protect, use a6=0, a1=1, a0=0. for chip unprotect, use a6=1, a1=1, a0=0. v id sa, a6,a1,a0 reset# 0 v t vidr t vidr >1
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 45 en29lv320a rev. b, issue date: 2007 / 07 / 17 erase and program performance limits parameter typ max unit comments sector erase time 0.5 10 sec chip erase time 70 sec excludes 00h programming prior to erasure byte programming time 8 300 s accelerated byte/word program time 7 200 s word programming time 8 300 s byte 35 100 chip programming time word 17 50 sec excludes system level overhead erase/program endurance 100k cycles minimum 100k cycles note: typical conditions are room temperature, 3v and checkboard pattern programmed. latch up characteristics parameter description min max input voltage with respect to v b ss b on all pins except i/o pins (including a9, reset and oe#) -1.0 v 12.0 v input voltage with respect to v b ss b on all i/o pins -1.0 v vcc + 1.0 v vcc current -100 ma 100 ma note: these are latch up characteristics and the device sh ould never be put under these conditions. refer to absolute maximum ratings for the actual operating limits. 48-pin tsop package capacitance parameter symbol parameter description test setup typ max unit c b in b input capacitance v b in b = 0 6 7.5 pf c b out b output capacitance v b out b = 0 8.5 12 pf c b in2 b control pin capacitance v b in b = 0 7.5 9 pf note: test conditions are temperature = 25c and f = 1.0 mhz. data retention parameter description test conditions min unit 150c 10 years minimum pattern data retention time 125c 20 years
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 46 en29lv320a rev. b, issue date: 2007 / 07 / 17 figure 13. tsop 12mm x 20mm
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 47 en29lv320a rev. b, issue date: 2007 / 07 / 17
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 48 en29lv320a rev. b, issue date: 2007 / 07 / 17 figure 14. 48tfbga package outline
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 49 en29lv320a rev. b, issue date: 2007 / 07 / 17 revisions list revision no description date a initial release 2006/11/06 b to correct the table 11. dc characteristics, i b cc4 (reset current) unit from ma to a in page 32 2007/07/17

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